Many challenges affect the ability to accurately predict the performance of circuit designs, particularly as integrated circuit (IC) fabrication process technologies migrate into sub-100 nanometer (nm) regions. Such challenges include, for example, circuit complexity, process variability and uncertainty, modeling uncertainty, variability in assumptions utilized in electronic design automation (EDA) tools, etc. In order to compensate for these uncertainties, changes that have been made to timing sign-off include signing off at specified minimum and maximum temperature corners and adding an extra margin onto the design. However, newer modeling obstacles, with varying degrees of influence, are becoming critical in achieving silicon accuracy in both analysis and implementation.
Using conventional circuit static timing analysis (STA) tools, it is assumed that circuit delay paths are fastest or slowest at specified minimum or maximum temperature corners. Traditionally, cell delay increases with rising temperature. But in sub-100 nm process designs, measurement has shown that cell delays can decrease with rising temperature. This behavior is often referred to as temperature inversion. Temperature inversion is dependent on various factors, including, for example, IC process parameters, circuit type, cell load, and supply voltage. At sub-100 nm, it has been observed that the extent of temperature dependency can vary differently with each type of cell and its load in the circuit, and such temperature dependency need not be uniform for all cells.
Conventional modeling and analysis tools have proved to be inadequate in terms of predicting circuit behavior for sub-100 nm process designs. Accordingly, there exists a need for techniques for improving the accuracy of circuit timing characterization that do not suffer from one or more of the above-described problems associated with conventional timing characterization methodologies.